One problem with Phase-Change Memory (PCM) devices is that activation current demands increase with the number of cells that are activated during a write operation. US Patent Application 2008/0101131, Ser. No. 11/790,146 for Lee et al., filed Apr. 24, 2007, for example, provides a PCM apparatus wherein new data that is to be written into cells is selectively inverted based on a comparison between pre-existing data and new data associated with a write command. A benefit of Lee is that fewer memory cells must be activated in many instances.
However, Lee requires an additional status bit (also known as a polarity bit or flip bit) for indicating whether the data has been inverted. If an error occurs in this status bit then all of the data bits which correspond to this status bit will be in error. This is especially critical when Error Correction Code (ECC) techniques are employed for mitigating the effects of errors caused by, for example, limited write endurance of PCM. ECC's, such as Hamming Codes, typically used in semiconductor memories can only correct single errors or detect double-bit errors. Hence, an error that occurs in the status bit is catastrophic compared to an error that occurs in the data bits.
A PCM having enhanced endurance and PCM with improved error tolerance is needed.